This patent relates generally to integrated circuit (IC) process technology and, more particularly, to a CMOS interconnection and method of interconnecting transistors that reduces the size of source/drain areas.
Leakage currents, parasitic capacitance, and switching speeds are all dependent on the size of the source/drain junction areas. To that end, research continues in the reduction of source/drain surface area and junction depth. Likewise, research continues to reduce the overall size of a transistor to increase transistor density in IC substrate.
Reducing the size of transistors is a goal dependent upon a number of factors. However, the necessity of interconnections between transistors, and between metal levels in an IC is at least one factor limiting size reduction. Connections to the source or drain of a transistor from another metal level are typically made with a via through an overlying interlevel dielectric. A metal, such as aluminum, fills the via to contact the underlying source or drain area. A trench or line intersects the via at the interlevel dielectric surface, and electrical communication is made from that line, through the via, to the transistor source/drain surface. Due to the resolution errors inherent in photolithographic masks, etching processes, and alignment, there are limits to how small a via diameter can only be made. Even a sub-micron sized via requires a relatively large source/drain surface area for electrical connection.
It would be advantageous if a transistor interconnection method could be devised that is not dependent on the surface area of the source/drain areas.
It would be advantageous if the interconnection between metal levels in an IC substrate was not made directly to the transistor source/drain regions.
It would be advantageous if the source and drain areas of a transistor could be reduced to minimize drain leakage current, without affecting connections to the source and drain regions.
Accordingly, a method is provided for forming interconnections from at least a first transistor with source/drain surface areas, through surrounding regions of field oxide. The method comprises the steps of:
a) depositing a semiconductor film, such as a silicon-germanium compound, over the transistor, including the source/drain surface areas and the surrounding field oxide regions; PA1 b) depositing a refractory metal layer over the semiconductor film, including the source/drain regions and selected adjoining areas of field oxide; and PA1 c) annealing the semiconductor film and refractory metal to form a silicide film overlying the source/drain surface areas and the selected adjoining areas of field oxide. An electrical connection is made to the source/drain regions from the surrounding field oxide region.
Typically, the transistor includes a gate electrode with an underlying gate oxide layer, and first oxide sidewalls overlying portions of the source/drain region. Then, Step b) includes depositing a semiconductor film overlying the gate electrode and first oxide sidewalls. Before the refractory metal is deposited, a layer of insulation, such as oxide, is deposited over the first semiconductor film. This oxide layer is anisotropically etched to remove the oxide on the source/drain surface areas, gate electrode, and surrounding field oxide region. Because of the highly directional anisotropically etching process, oxide is not removed from the gate electrode sidewalls, so that a second sidewall is formed. Then, Step b) includes depositing refractory metal over the gate electrode and the second sidewalls. Step c) includes annealing the transistor to form a silicide film where the semiconductor film is exposed. A silicide film is, therefore, not formed on the second sidewalls.
After annealing, unreacted refractory metals, the second sidewalls, and the first semiconductor film overlying the first oxide sidewalls are removed. A dielectric interlevel is deposited over the transistor. Contact holes are etched through the dielectric interlevel to the silicide film overlying the selected areas of field oxide. Metal is deposited in the contact holes to form electrical interconnect between the transistor source/drain regions and the surface of the dielectric interlevel. In this manner, connections are made to the transistor without regard to the size of the source/drain surface areas.
In a similar manner, a strap interconnection is formed between the source/drain regions of a second transistor and the source/drain regions of a first transistor on the same metal level across a field oxide region. Step a) includes depositing a semiconductor film over both transistors. Step b) deposits refractory metal over the source/drain surface areas and selected areas of intervening field oxide. Steps c) anneals the semiconductor film and refractory metal to form a silicide film overlying the source/drain of the second transistor, the source/drain of the first transistor, and the selected areas of intervening field oxide. In this manner, electrical interconnections are made from the first transistor to the second transistor across the intervening field oxide. For example, the drain of the first transistor is connected to the source of the second transistor.
A CMOS interconnection and CMOS interconnection product by process are also provided. The CMOS interconnection comprises source/drain areas and field oxide regions surrounding the source/drain regions. The CMOS interconnection also comprises a gate electrode with first oxide sidewalls. A silicide film overlies the source/drain surface areas and selected adjoining field oxide regions. The silicide layer is formed by depositing a layer semiconductor film overlying the transistor and surrounding field oxide regions. Then, an insulator layer is deposited and anisotropically etched to form second gate electrode sidewalls. Refractory metal is deposited over the transistor and selected adjoining areas of field oxide and annealed to form a silicide film. Unreacted refractory metal, the second sidewalls, and the semiconductor film overlying the first oxide sidewalls are removed. Electrical connections can be made to the transistor source/drain surface areas through the silicide film overlying the field oxide selected areas.